made a test work

hwdriver/SCA.py

@@ -126,7 +126,82 @@ class Sca (Utils, Roc):
 
             return 0
     # --------------------------------------------------------------------------------
+    # --------------------------------------------------------------------------------
+    def rdstr(self, debug=None):
+        """
+        Read the feedback from the SCA component
+        """
+        err_cnt = 0
+        err_int = 64
+        while (err_int != 0):
+            data = self.rocRd(self.rd_add_data, debug)
+            cmd = self.rocRd(self.rd_add_cmd, debug)
+            ctrl = self.rocRd(self.rd_add_ctr, debug)
+
+            err_code = hex(cmd & 0xff)
+            err_int = int(err_code, 0)
 
+            tr_id = (cmd >> 16) & 0xff
+            if (tr_id == 0):
+                print('MAJOR ERROR ')
+                z.log('MAJOR ERROR, tr_id == 0', Errlvl.CRITICAL)
+                return 1
+
+            if err_int == 64:
+                # CH BUSY
+                time.sleep(1.0/1000.0)
+            elif err_int != 0:
+                # ERROR
+                err_cnt += 1
+                self.error(err_code)
+                time.sleep(1.0/100.0)
+                return 1
+            else:
+                pass
+                return "RD - DATA {} CH {} TR {} ERR {} CTRL {}".format(hex(data), hex(cmd >> 24), hex((cmd >> 16) & 0xff), hex(cmd & 0xff), hex(ctrl))
+#print('RD - DATA %10s CH %4s TR %4s ERR %4s CTRL %4s' % (hex(data), hex(cmd >> 24), hex((cmd >> 16) & 0xff), hex(cmd & 0xff), hex(ctrl)))
+
+            return 0
+    # --------------------------------------------------------------------------------
+    
+    # --------------------------------------------------------------------------------
+    def readbin(self, debug=None):
+        """
+        Return binary data from sca
+        """
+        err_cnt = 0
+        err_int = 64
+        while (err_int != 0):
+            data = self.rocRd(self.rd_add_data, debug)
+            cmd = self.rocRd(self.rd_add_cmd, debug)
+            ctrl = self.rocRd(self.rd_add_ctr, debug)
+
+            err_code = hex(cmd & 0xff)
+            err_int = int(err_code, 0)
+
+            tr_id = (cmd >> 16) & 0xff
+            if (tr_id == 0):
+                print('MAJOR ERROR ')
+                z.log('MAJOR ERROR, tr_id == 0', Errlvl.CRITICAL)
+                return 1
+
+            if err_int == 64:
+                # CH BUSY
+                time.sleep(1.0/1000.0)
+            elif err_int != 0:
+                # ERROR
+                err_cnt += 1
+                self.error(err_code)
+                time.sleep(1.0/100.0)
+                return 1
+            else:
+                return "{0:032b}".format(data)
+#                return "RD - DATA {} CH {} TR {} ERR {} CTRL {}".format(hex(data), hex(cmd >> 24), hex((cmd >> 16) & 0xff), hex(cmd & 0xff), hex(ctrl))
+#print('RD - DATA %10s CH %4s TR %4s ERR %4s CTRL %4s' % (hex(data), hex(cmd >> 24), hex((cmd >> 16) & 0xff), hex(cmd & 0xff), hex(ctrl)))
+
+            return 0
+    # --------------------------------------------------------------------------------
+    
     # --------------------------------------------------------------------------------
     def exe(self, debug=None):
         """

jtag_if/jtag_io.py

@@ -33,5 +33,12 @@ def write128(tms_bits, tdi_bits, sca):
     sca.wr(SCARegs['JTAG_GO'], 0)
     pass
 
-def read128():
-    pass    
+def read128(sca):
+    data=[]
\ No newline at end of file
+    for reg in settings.TDIregs: # naming of SCA regs is incoherent with the svf standard
+        sca.wr(cmd = reg, data = 0)
+        data.append(sca.readbin())
+    s=""
+    datastring = s.join(data)
+    return datastring
+#        data.append(sca.)
\ No newline at end of file

jtag_if/jtag_sequencer.py

@@ -6,7 +6,7 @@ Created on Fri Apr  6 11:28:43 2018
 """
 
  
-from jtag_if.jtag_io import write128
+from jtag_if.jtag_io import write128, read128
  
 FIFOLEN = 128
 
@@ -14,6 +14,7 @@ class Seq():
     def __init__(self,sca):
         self.tms_bits = ""
         self.tdi_bits = ""
+        self.tdo_bits = ""
         self.sca = sca
         
     def check_to_run(self,length):
@@ -22,6 +23,7 @@ class Seq():
             
     def call_run(self,length):
         write128(self.tms_bits[:FIFOLEN],self.tdi_bits[:FIFOLEN],self.sca)
+        self.tdo_bits += read128(self.sca)
         self.tms_bits = self.tms_bits[FIFOLEN:] 
         self.tdi_bits = self.tdi_bits[FIFOLEN:]
         self.check_to_run(length - FIFOLEN)

libReadoutCard.py

@@ -35,7 +35,7 @@ class BarChannel:
         print("closing barchannel")
         z.log("closing barchannel with {} reads and {} writes".format(self.readcount, self.writecount), Errlvl.INFO)
         z.log("final register configuration:",Errlvl.INFO)
-        z.log("{}".format(self.registers), Errlvl.INFO)
+        z.log(get_hex_registers(self.registers), Errlvl.INFO)
 
 
     def readregisterlist(self, reglist: dict):
@@ -60,4 +60,16 @@ class BarChannel:
         self.writecount += 1
         z.log("ROC-WRITE REG: {} DATA: {}".format(hex(register), hex(data)), Errlvl.DEBUG0)
         self.registers[register] = data
-        return None
+        return None
\ No newline at end of file
+    
+def get_hex_registers(registers : dict):
+    """takes a dict and formats the keys and values to hex"""
+    keys = ["{0:08x}:".format(key) for key in registers.keys()]
+    S = " "
+    values = ["{0:08x},\n".format(value) for value in registers.values()]
+#    keyval[::2] = keys#[val for pair in zip(keys,values) for val in pair] #https://stackoverflow.com/users/367273/npe
+#    keyval[1::2] = values
+    keyval = [val for pair in zip(keys,values) for val in pair] # interleave
+    keyvalstring = S.join(keyval)
+    return keyvalstring
+    
\ No newline at end of file

svf_intepreter.py

@@ -71,7 +71,7 @@ class bussequencer():
                  + self.bus.SDR.D
                  + self.bus.TDR.D)
         tms_s_a = jtg_tp.state_change('DRSHIFT')
-        tms_s_b = jtg_tp.state_change(self.ENDDR)
+        tms_s_b = jtg_tp.state_change(self.ENDDR) # TODO  possible bug. we might want to continue to add data.
         
         tms_s = (tms_s_a
             + "0" * len(tdi_d_s)
@@ -81,7 +81,7 @@ class bussequencer():
                 + tdi_d_s
                 + "0" * len(tms_s_b))
         
-        self.jtg_seq.queue(tms_s, tdi_s)
+        self.jtg_seq.queue(tms_s, tdi_s) # queues bit sequence...
 
     def scan_ir(self):
 #        self.jtg.scan_ir(self.bus.HIR.D, self.bus.SIR.D,

tests/test_svf_interpreter.py

@@ -6,7 +6,8 @@ Created on Wed Mar 21 15:49:30 2018
 """
 
 import svf_intepreter as interpreter
-
+from settings import z
+from hwdriver.SCA import Sca
 
 def space():
     """prints this"""
@@ -16,6 +17,12 @@ def space():
 def littlespace():
     """prints this"""
     print("------")
+    
+    
+id_card = 1
+gbt_ch = 0
+board = "CRU"
+sca = Sca(id_card, 2, gbt_ch, board, logger = z)
 
 
 testvector = [
@@ -34,7 +41,7 @@ testvector = [
     ['SDR', '1056', ['TDI', '924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924924']],
     ['STATE', 'IDLE'],
 ]
-svf = interpreter.svfinterpreter()
+svf = interpreter.svfinterpreter(logger =z , sca=sca)
 space()
 for test in testvector:
  #   print("testing", test)